TSMC Unveils Affordable 4nm N4C Process, Targeting 8.5% Cost Cut by 2025

TSMC introduces N4C, an optimized 5nm-class node with reduced costs and improved yields, demonstrating their commitment to refining existing process technologies and providing cost-effective options for chipmakers.

Optimized 5nm-class node with potential for smaller die sizes
Potential for up to 8.5% decrease in die costs
Expected to achieve high volume and yields right from the start

TSMC, the leading semiconductor manufacturer, is not only focused on its nodes like N3E and N2. The company recognizes the ongoing demand for chips made using more mature process technologies. That’s why TSMC has been refining its existing nodes, including its current-generation 5nm-class products. At the recent North American Technology Symposium 2024, TSMC launched its latest addition to the 5nm-class family: N4C.

N4C is an optimized 5nm-class node that builds upon the advancements of N4P, the most advanced technology in this family. TSMC aims to reduce manufacturing costs further with N4C by implementing changes such as rearchitecting standard cell and SRAM cell, modifying design rules, and reducing the number of masking layers. These improvements are expected to result in smaller die sizes and reduced production complexity, leading to up to an 8.5% decrease in die costs. Additionally, N4C offers higher functional yields due to its die area reduction while maintaining the same wafer-level defect density rate as N4P.

Kevin Zhang, Vice President of Business Development at TSMC, emphasized that the company’s focus on 5nm and 4nm technologies is far from over. With N4C, TSMC provides customers with the opportunity to reduce costs by eliminating some masks and improving IP design. By leveraging the same design infrastructure as N4P, chipmakers can find the right balance between cost benefits and design effort when adopting a 4nm-class process technology like N4C.

The introduction of N4C coincides with TSMC’s chip design customers preparing to launch products based on the company’s final generation of FinFET process technology, the 3nm N3 series. While N3 is expected to be successful, the high costs associated with N3B have raised concerns. N4C could serve as an attractive alternative, offering a cost-effective FinFET node with potential longevity.

TSMC plans to commence volume production of N4C chips in the coming year. Given TSMC’s extensive experience in producing 5nm-class chips for nearly five years, N4C is expected to achieve high volume and yields right from the start.

In conclusion, TSMC’s introduction of the N4C node demonstrates its commitment to refining existing process technologies and providing cost-effective options for chipmakers. With its potential to deliver smaller die sizes, reduced complexity, and improved yields, N4C could become a significant and long-lasting node in TSMC’s portfolio.

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Background Information

About TSMC: TSMC, or Taiwan Semiconductor Manufacturing Company, is a semiconductor foundry based in Taiwan. Established in 1987, TSMC is a important player in the global semiconductor industry, specializing in the manufacturing of semiconductor wafers for a wide range of clients, including technology companies and chip designers. The company is known for its semiconductor fabrication processes and plays a critical role in advancing semiconductor technology worldwide.