Revolutionary Zero ASIC Chip Empowers Widespread Access to Chip Manufacturing

Zero ASIC has revolutionized traditional chip design with their ChipMaker platform, offering a 100X reduction in chip development costs and 3D chiplet composability, automated no-code chiplet-based chip design, and zero-install interactive RTL-based chip emulation.

ChipMaker platform showcases several world-first achievements, including 3D chiplet composability, fully automated no-code chiplet-based chip design, and zero-install interactive RTL-based chip emulation.
ChipMaker platform revolutionizes traditional chip design, which typically costs over $100 million and requires expert teams to spend 2-3 years to go from concept to production.
eBrick 3D chiplets enable plug-and-play chiplet composability.

Zero ASIC, a semiconductor startup, has emerged from stealth mode with an exciting announcement about its ChipMaker platform. This platform showcases several world-first achievements, including 3D chiplet composability, fully automated no-code chiplet-based chip design, and zero-install interactive RTL-based chip emulation. Moreover, Zero ASIC has laid out an ambitious roadmap to achieve a remarkable 100X reduction in chip development costs.

Andreas Olofsson, CEO and founder of Zero ASIC, explains the significance of Custom Application Specific Integrated Circuits (ASICs) in offering a significant cost and energy advantage over commercial off-the-shelf devices. However, the exorbitant development costs associated with ASICs have made them unfeasible for most applications. To overcome this barrier, Zero ASIC’s mission is to simplify the process of ordering an ASIC to the level of ordering catalog parts from an electronics distributor.

The ChipMaker Platform developed by Zero ASIC revolutionizes traditional chip design, which typically costs over $100 million and requires expert teams to spend 2-3 years to go from concept to production. By leveraging chiplet-based design, Zero ASIC addresses both the time and cost challenges associated with custom ASICs. The platform allows users to design, validate, and assemble System-in-Packages using a catalog of pre-validated chiplets. With the help of cloud FPGAs, users can test their custom designs quickly and accurately before ordering physical devices.

To address the limitations of existing 2D/2.5D chiplet design approaches, Zero ASIC introduces eFabric, an active grid-like 3D interposer. This innovative technology enhances die-to-die communication efficiency and composability. The eFabric enables integration of ultra-critical processing blocks using 3D attached eBrick chiplets and off-package IO functions using 2D attached ioBrick chiplets. With these advancements, Zero ASIC achieves unprecedented levels of chiplet-based performance and flexibility.

Zero ASIC’s eBrick 3D chiplets play a crucial role in enabling plug-and-play chiplet composability. These chiplets adhere to a set of electrical and mechanical 3D chiplet standards specifications. Some examples of eBricks include a quad-core RISC-V Linux capable dual-issue processor, a 5K LUT embedded FPGA, and a 3MB SRAM -3 TOPS machine learning accelerator.

Zero ASIC’s composable chiplet ASICs find their ideal applications in various sectors facing energy and supply chain challenges. These include robotics, automotive safety, aerospace and defense, 5G/6G communication, test and measurement, software-defined radio, smart manufacturing, medical diagnostics, and high-performance computing.

The ChipMaker design and emulation platform is available for immediate access on zeroasic.com. Additionally, Zero ASIC will be showcasing live demonstrations of the ChipMaker platform at the Open Compute Platform Summit (Open Chiplet Economy Center) from October 17-19 in SAN Jose, CA. Customized ASICs are expected to begin sampling in Q3 2024.

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