TSMC’s 2nm Tech: N2 Set for 2025, N2P Drops Backside Power, and NanoFlex Enhances Cell Efficiency

Taiwan Semiconductor Manufacturing Co. (TSMC) recently shared some exciting updates on its upcoming process technologies during the North American Technology Symposium 2024. The company remains on track with its plans for the 2 nm node, with volume production expected to begin in the second half of 2025. Following that, the N2P node will succeed N2 in late 2026, although it won’t include the previously announced backside power delivery capabilities. However, TSMC will introduce a new feature called NanoFlex across its entire N2 family, allowing chip designers to optimize performance, power, and area by mixing and matching cells from different libraries.

NanoFlex is a significant development for TSMC’s N2 family of production nodes, which includes N2, N2P, and N2X. This technology empowers chip designers to fine-tune their designs by utilizing cells from various libraries, such as high performance, low power, and area efficiency. TSMC’s existing N3 fabrication process already supports a similar capability called FinFlex, but NanoFlex brings additional benefits due to the use of gate-all-around (GAAFET) nanosheet transistors in the N2 node. With NanoFlex, TSMC can optimize channel width for performance and power, allowing the creation of short cells for efficiency or tall cells for higher performance gains of up to 15%.

In terms of timeline, TSMC plans to begin risk production of the N2 node in 2025 and move into high-volume manufacturing in the second half of the same year. This suggests that we can expect devices with N2 chips to hit the market in 2026. Compared to the N3E node, TSMC anticipates that N2 will deliver a 10% to 15% increase in performance at the same power level or reduce power consumption by 25% to 30% at the same frequency and complexity. Additionally, TSMC aims for a 15% density increase with N2, which showcases impressive scaling capabilities.

Following N2, TSMC has plans for the performance-enhanced N2P and voltage-enhanced N2X nodes in 2026. Initially, TSMC had announced that N2P would feature a backside power delivery network (BSPDN), but it seems the company has decided against it to avoid additional costs. Instead, regular power delivery circuitry will be used for N2P, while the advanced feature will be reserved for TSMC’s next-generation node, available to customers in late 2026.

Notably, the N2 node will introduce a significant innovation in power-related technology: super-high-performance metal-insulator-metal (SHPMIM) capacitors. These capacitors aim to enhance power supply stability and offer more than double the capacity density of TSMC’s existing super-high-density metal-insulator-metal (SHDMIM) capacitors. Furthermore, the SHPMIM capacitor reduces sheet resistance and via resistance by 50% compared to its predecessor.

TSMC’s updates on its upcoming process technologies showcase its commitment to pushing boundaries and delivering improved performance, power efficiency, and area optimization. The introduction of NanoFlex and the advancements in power-related innovations highlight TSMC’s dedication to meeting the evolving needs of chip designers and enabling the development of devices.

(Source)

Background Information

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About TSMC: TSMC, or Taiwan Semiconductor Manufacturing Company, is a semiconductor foundry based in Taiwan. Established in 1987, TSMC is a important player in the global semiconductor industry, specializing in the manufacturing of semiconductor wafers for a wide range of clients, including technology companies and chip designers. The company is known for its semiconductor fabrication processes and plays a critical role in advancing semiconductor technology worldwide.