JEDEC Enhances DDR5 Specification to Bolster Security against Rowhammer Attacks, Introduces DDR5-8800

April 23, 2024 by our News Team

The JEDEC Solid State Technology Association has released the latest version of the DDR5 SDRAM standard, JESD79-5C, which includes new features such as Per-Row Activation Counting and an expansion of timing parameters, to improve reliability, security, and performance in various applications.

  • Enhanced data integrity through Per-Row Activation Counting (PRAC)
  • Faster data transfer rates with expanded timing parameters
  • Commitment to security with the deprecation of Partial Array Self Refresh (PASR)

The JEDEC Solid State Technology Association, known for its role in setting industry standards for microelectronics, has just released the latest version of the DDR5 SDRAM standard, called JESD79-5C. This update brings a host of new features aimed at improving reliability, security, and performance across various applications, including high-performance servers and emerging technologies like AI and machine learning.

One of the key additions to the standard is Per-Row Activation Counting (PRAC), a novel solution that enhances DRAM data integrity. PRAC keeps a precise count of DRAM activations on a wordline level. When an excessive number of activations is detected, the system is alerted to pause traffic and take necessary measures to mitigate any potential issues. This coordination between the DRAM and the system ensures a more accurate and predictable approach to addressing data integrity challenges.

JESD79-5C also brings other notable features to the table. This includes an expansion of timing parameters definition from 6800 Mbps to 8800 Mbps, allowing for faster data transfer rates. Additionally, DRAM core timings and Tx/Rx AC timings have been extended to support up to 8800 Mbps, compared to the previous version which only supported up to 6400 timing parameters and partial pieces up to 7200 DRAM core timings. The standard also introduces Self-Refresh Exit Clock Sync for I/O Training Optimization and incorporates Dual-Die Package (DDP) timings.

To address security concerns, JESD79-5C has deprecated Partial Array Self Refresh (PASR). This decision reflects the industry’s commitment to ensuring robust security measures across all aspects of the DDR5 standard.

Mian Quddus, Chairman of JEDEC Board of Directors, expressed his satisfaction with the collaborative efforts put forth by JEDEC’s JC-42 Committee for Solid State Memory in advancing the DDR5 standard. He emphasized that the features introduced in JESD79-5C are designed to meet the ever-evolving demands for security, reliability, and performance in a wide range of applications.

Christopher Cox, Chair of the JC-42 Committee, highlighted the significance of PRAC as a comprehensive solution to ensure DRAM data integrity. He also mentioned that efforts are underway to incorporate this feature into other DRAM product families within JEDEC, further extending its benefits across the industry.

With the release of JESD79-5C, JEDEC continues to drive innovation and set the bar high for standards in the microelectronics industry. This latest update is poised to make a significant impact on the performance and security of DDR5 SDRAM, catering to the needs of diverse applications and paving the way for future advancements in technology.

JEDEC Enhances DDR5 Specification to Bolster Security against Rowhammer Attacks, Introduces DDR5-8800

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Background Information

About JEDEC: JEDEC is the global leader in the development of standards for the microelectronics industry. It was founded in 1958 as the Joint Electron Device Engineering Council to develop standards for the microelectronics industry. The organization's headquarters is located in Arlington, Virginia, United States. JEDEC sets standards for a wide range of technologies, including semiconductors, memory devices, integrated circuits, and more. Its standards are widely adopted and utilized throughout the industry to ensure compatibility and interoperability among various electronic devices and components.

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Technology Explained

DDR5: DDR5 (Double Data Rate 5) is the next generation of memory technology for the computer industry. It is a modern day improvement on earlier DDR technologies, with faster speeds, greater bandwidth and higher capacities. DDR5 enables higher resolution, seamless gaming experiences and faster data transfer rates, making it an ideal choice for high-performance computing and 4K gaming. With its greater RAM compatibility, DDR5 provides faster buffering times and raised clock speeds, giving users an improved overall work system. DDR5 is also optimized for multi-tasking, allowing users to multitask without experiencing a significant drop in performance, increasing the productivity of digital tasks. As an ever-evolving technology, DDR5 is paving the way for the computer industry into a new and powerful era.

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