TSMC’s 3nm N3P Process Aims for Mass Production in 2022, Promising Enhanced Performance

TSMC is on track to enter mass production of its N3P process, an optical shrink of its current-generation N3E process, in the second half of 2024, bringing increased performance efficiency and transistor density, and demonstrating the company's commitment to pushing the boundaries of semiconductor technology.

On track for mass production in second half of 2024
Great yields on second-generation 3nm-class process
4% increase in performance or 9% reduction in power consumption with N3P

TSMC, one of the leading semiconductor manufacturers, provided an update on its 3nm-class processes during its spring technology symposium series. The company announced that its N3P process, an optical shrink of its current-generation N3E process, is on track to enter mass production in the second half of 2024. This development is expected to bring increased performance efficiency and transistor density compared to N3E.

TSMC has already achieved volume production of N3E and is reporting “great” yields on this second-generation 3nm-class process. The defect density of N3E is comparable to the older N5 node at the same point in its lifecycle, which is a notable achievement considering the challenges of developing finer generations of FinFET technology. This success allows TSMC’s customers, like Apple with its M4 SoC, to benefit from the improved process node quickly.

N3E is a relaxed version of N3B, eliminating some EUV layers and avoiding the use of EUV double patterning. While this makes it slightly cheaper to produce and can improve yields in certain cases, it does come at the cost of reduced transistor density.

Looking ahead, TSMC’s N3P has completed qualification and is showing similar yield performance to N3E. As an optical shrink, N3P enables processor developers to achieve a 4% increase in performance at the same leakage or a 9% reduction in power consumption at the same clocks. Additionally, it offers a 4% boost in transistor density for mixed chip designs.

N3P is set to be production ready in the second half of this year, and TSMC expects it to be widely adopted by chip designers. It is compatible with N3E in terms of IP blocks, process rules, EDA tools, and design methodology, making it a logical choice for new tape outs. The advantages of N3P, including higher performance efficiency at a lower cost, make it an attractive option for chip designers.

Overall, TSMC’s progress with its 3nm-class processes, particularly the upcoming N3P, demonstrates the company’s commitment to pushing the boundaries of semiconductor technology. With mass production on the horizon, we can expect to see even more advanced and efficient chips in the near future.

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Background Information

About Apple:

Apple Inc., known for its iconic products, was founded by Steve Jobs, Steve Wozniak, and Ronald Wayne in 1976. The company has since revolutionized the technology landscape with innovations like the Macintosh computer, iPod, iPhone, iPad, and more. for its emphasis on design, user experience, and ecosystem integration, Apple's devices and software have made a profound impact on various industries. With a commitment to quality and innovation, Apple remains a global technology leader.

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About TSMC:

TSMC, or Taiwan Semiconductor Manufacturing Company, is a semiconductor foundry based in Taiwan. Established in 1987, TSMC is a important player in the global semiconductor industry, specializing in the manufacturing of semiconductor wafers for a wide range of clients, including technology companies and chip designers. The company is known for its semiconductor fabrication processes and plays a critical role in advancing semiconductor technology worldwide.

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Technology Explained

EDA: EDA stands for Electronic Design Automation, and it refers to a category of software tools and solutions used in the design and development of electronic systems and integrated circuits. EDA tools assist engineers and designers in creating complex electronic designs, from individual components to entire systems, by automating various aspects of the design process. These tools encompass a wide range of functionalities, including schematic capture, simulation, layout design, verification, and testing.

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EUV: Extreme Ultraviolet Lithography (EUV or EUVL) is an advanced semiconductor manufacturing technique that employs extremely short wavelengths of light in the extreme ultraviolet spectrum to create intricate patterns on silicon wafers. Utilizing a wavelength around 13.5 nanometers, significantly shorter than traditional lithography methods, EUVL enables the production of smaller and more densely packed integrated circuits, enhancing the performance and efficiency of modern microprocessors and memory chips.

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SoC: A System-on-Chip (SoC) is a highly integrated semiconductor device that encapsulates various electronic components, including processors, memory, input/output interfaces, and often specialized hardware components, all on a single chip. SoCs are designed to provide a complete computing system or subsystem within a single chip package, offering enhanced performance, power efficiency, and compactness. They are commonly used in a wide range of devices, from smartphones and tablets to embedded systems and IoT devices, streamlining hardware complexity and facilitating efficient integration of multiple functions onto a single chip.