TSMC’s 3D Stacked SoIC Packaging Advances Rapidly, Aims for Ultra-Dense 3μm Pitch by 2027


May 31, 2024 by our News Team

icle; Die Orientation - face-to-face; Qualification Time - Q4 2026 for mobile SoC TSMC is making significant progress in advancing its 3D-stacked SoIC packaging technology, with plans to reduce bump pitch and increase performance for high-performance computing applications. TSMC is advancing its 3D-stacked SoIC packaging technology, with plans to reduce bump pitch and increase performance for high-performance computing applications by 2027.

icle; Die Orientation - face-to-face; Qualification Time - Q4 2026 for mobile SoC

  • Significant reduction in bump pitch from 9μm to 3μm by 2027
  • Potential for increased bandwidth density and overall chip performance
  • Empowering high-performance computing customers to develop large and ultra-dense processor designs


TSMC, the leading semiconductor manufacturer, is making significant strides in advancing its 3D-stacked system-on-integrated chips (SoIC) packaging technology. During a recent technology symposium, TSMC launched its roadmap for the future of SoIC, outlining plans to reduce the bump pitch from the current 9μm to an impressive 3μm by 2027. This evolution will involve combining A16 and N2 dies in increasingly compact configurations.

Among TSMC’s array of advanced packaging technologies, the most intriguing and complex is the 3D-stacked SoIC. This method, which employs hybrid wafer bonding, allows for the direct stacking of two advanced logic devices. The result is an ultra-dense and ultra-short connection between the chips, primarily targeted at high-performance applications. Currently, SoIC-X (bumpless) is utilized in select applications such as AMD’s 3D V-cache technology for CPUs and Instinct MI300-series AI products. However, the technology’s potential is limited by constraints on die sizes and interconnection pitches.

Fortunately, TSMC has ambitious plans to overcome these limitations. The company expects its SoIC-X technology to advance rapidly, enabling the assembly of a chip that pairs a reticle-sized top die made on TSMC’s A16 (1.6nm-class) with a bottom die produced using TSMC’s N2 (2nm-class) by 2027. These dies will be connected using 3μm bond pitch silicon vias (TSVs), which are three times denser than the current 9μm pitch. This significant reduction in interconnection size will allow for a much larger number of connections, resulting in a substantial increase in bandwidth density and overall chip performance.

TSMC’s SoIC-X roadmap showcases the planned advancements:

– 2022: Top Die – N7; Bottom Die – N7; Bond Pitch – 9μm; Size – 0.1 reticle
– 2023: Top Die – N5; Bottom Die – ≥N6; Bond Pitch – 9μm; Size – 0.4 reticle
– 2024: Top Die – N4; Bottom Die – ≥N5; Bond Pitch – 6μm; Size – 0.8 reticle
– 2025: Top Die – N4; Bottom Die – ≥N4; Bond Pitch – 6μm; Size – 1 reticle
– 2026: Top Die – N2; Bottom Die – ≥N3; Bond Pitch – 4.5μm; Size – 1 reticle
– 2027: Top Die – A16; Bottom Die – ≥N2; Bond Pitch – 3μm; Size – 1 reticle

These improved hybrid bonding techniques aim to empower TSMC’s high-performance computing (HPC) customers, including AMD, Broadcom, Intel, and nVidia, to develop large and ultra-dense disaggregated processor designs for demanding applications. The technology’s ability to minimize the distance between dies and optimize floor space usage is critical in these scenarios. Additionally, for applications where performance is paramount, multiple SoIC-X packages can be placed on a CoWoS interposer to achieve enhanced performance while consuming less power.

In addition to the bumpless SoIC-X packaging technology, TSMC is also working on the bumped SoIC-P packaging process. SoIC-P is designed for more cost-effective applications that still require 3D-stacking but do not necessitate the additional performance and complexity of bumpless copper-to-copper TSV connections. This approach will enable a broader range of companies to leverage SoIC, potentially making it accessible for cost-conscious consumer applications.

According to TSMC’s current plans, by 2025, the company will introduce face-to-back (F2B) bumped SoIC-P technology capable of pairing a 0.2-reticle sized N3 (3nm-class) top die with an N4 (4nm-class) bottom die. These dies will be connected using 25μm pitch microbumps (µbumps). In 2027, TSMC will launch bumped face-to-face (F2F) SoIC-P technology, enabling the placement of an N2 top die on an N3 bottom die with a pitch of 16μm.

TSMC’s SoIC-P roadmap outlines the following developments:

– 2025: Top Die – N3; Bottom Die – ≥N4; Bond Pitch – 25μm; Size – 0.2 reticle; Die Orientation – face-to-back; Qualification Time – Q4 2024 for mobile SoC
– 2027: Top Die – N2; Bottom Die – ≥N3; Bond Pitch – 16μm; Size – 0.4 ret

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Background Information


About AMD:

AMD, a large player in the semiconductor industry is known for its powerful processors and graphic solutions, AMD has consistently pushed the boundaries of performance, efficiency, and user experience. With a customer-centric approach, the company has cultivated a reputation for delivering high-performance solutions that cater to the needs of gamers, professionals, and general users. AMD's Ryzen series of processors have redefined the landscape of desktop and laptop computing, offering impressive multi-core performance and competitive pricing that has challenged the dominance of its competitors. Complementing its processor expertise, AMD's Radeon graphics cards have also earned accolades for their efficiency and exceptional graphical capabilities, making them a favored choice among gamers and content creators. The company's commitment to innovation and technology continues to shape the client computing landscape, providing users with powerful tools to fuel their digital endeavors.

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About Broadcom:

Founded in 1961, Broadcom is a leading global technology company headquartered in the United States. They specialize in semiconductor and infrastructure software solutions. Broadcom's innovations in connectivity, networking, and storage technologies have made them a key player in the industry, with a focus on enabling seamless communication and connectivity in the digital world.

Broadcom website  Broadcom LinkedIn
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About Intel:

Intel Corporation, a global technology leader, is for its semiconductor innovations that power computing and communication devices worldwide. As a pioneer in microprocessor technology, Intel has left an indelible mark on the evolution of computing with its processors that drive everything from PCs to data centers and beyond. With a history of advancements, Intel's relentless pursuit of innovation continues to shape the digital landscape, offering solutions that empower businesses and individuals to achieve new levels of productivity and connectivity.

Intel website  Intel LinkedIn
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About nVidia:

NVIDIA has firmly established itself as a leader in the realm of client computing, continuously pushing the boundaries of innovation in graphics and AI technologies. With a deep commitment to enhancing user experiences, NVIDIA's client computing business focuses on delivering solutions that power everything from gaming and creative workloads to enterprise applications. for its GeForce graphics cards, the company has redefined high-performance gaming, setting industry standards for realistic visuals, fluid frame rates, and immersive experiences. Complementing its gaming expertise, NVIDIA's Quadro and NVIDIA RTX graphics cards cater to professionals in design, content creation, and scientific fields, enabling real-time ray tracing and AI-driven workflows that elevate productivity and creativity to unprecedented heights. By seamlessly integrating graphics, AI, and software, NVIDIA continues to shape the landscape of client computing, fostering innovation and immersive interactions in a rapidly evolving digital world.

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About TSMC:

TSMC, or Taiwan Semiconductor Manufacturing Company, is a semiconductor foundry based in Taiwan. Established in 1987, TSMC is a important player in the global semiconductor industry, specializing in the manufacturing of semiconductor wafers for a wide range of clients, including technology companies and chip designers. The company is known for its semiconductor fabrication processes and plays a critical role in advancing semiconductor technology worldwide.

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Technology Explained


CoWoS: CoWoS, or Chip-on-Wafer-on-Substrate, is a recent advancement in chip packaging that allows for more powerful processors in a compact size. This technology stacks multiple chips on a silicon interposer, enabling denser connections and improved performance. Developed for high-performance computing, CoWoS promises faster processing, lower power consumption, and the ability to pack more processing power into smaller devices.

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HPC: HPC, or High Performance Computing, is a type of technology that allows computers to perform complex calculations and process large amounts of data at incredibly high speeds. This is achieved through the use of specialized hardware and software, such as supercomputers and parallel processing techniques. In the computer industry, HPC has a wide range of applications, from weather forecasting and scientific research to financial modeling and artificial intelligence. It enables researchers and businesses to tackle complex problems and analyze vast amounts of data in a fraction of the time it would take with traditional computing methods. HPC has revolutionized the way we approach data analysis and has opened up new possibilities for innovation and discovery in various fields.

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SoC: A System-on-Chip (SoC) is a highly integrated semiconductor device that encapsulates various electronic components, including processors, memory, input/output interfaces, and often specialized hardware components, all on a single chip. SoCs are designed to provide a complete computing system or subsystem within a single chip package, offering enhanced performance, power efficiency, and compactness. They are commonly used in a wide range of devices, from smartphones and tablets to embedded systems and IoT devices, streamlining hardware complexity and facilitating efficient integration of multiple functions onto a single chip.

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