Andes introduces the AndesCore RISC-V Multicore Vector Processor AX45MPV

Andes Technology, a important provider of energy-efficient 32/64-bit RISC-V processor cores and a founding member of RISC-V International, has announced the general availability of its latest offering, the AndesCore AX45MPV multicore vector processor IP. This marks the third generation of the highly acclaimed AndesCore vector processor series. The AX45MPV is designed to cater to applications that deal with large volumes of data, such as ADAS, AI inference and training, AR/VR, multimedia, robotics, and signal processing.

Andes Technology began collaborating with Meta on datacenter AI using RISC-V vector core in early 2019. Later in the year, they launched the AndesCore NX27V, which became the industry’s first commercial RISC-V vector processor core capable of generating up to 4 512-bit vector results per cycle. This breakthrough caught the attention of SoC design teams worldwide working on AI accelerators and has since been adopted in over a dozen datacenter AI projects. The RISC-V vector processor cores have now become the preferred choice for ML and AI chip vendors.

With the aim of further enhancing compute density, the AX45MPV builds upon the capabilities of its predecessor, the NX27V, by extending the dual-issue 8-stage pipeline, Linux support, and multicore features. While the AX45MPV primarily functions as a Linux application processor with datacenter-grade AI capabilities, it can also be utilized as an efficient and powerful compute processor in processing elements (PEs) within a large compute array. The AX45MPV offers significant performance improvements over its predecessor, with up to 6 1024-bit vector results per cycle, resulting in more than 3 times the performance. To fully leverage its enhanced computation power, the AX45MPV provides two 1024-bit memory interfaces. It also introduces a new high-bandwidth vector local memory (HVM) option, which includes 1 or 2 HVM bank ports for efficient vector loads/stores, as well as an external DMA engine for seamless data movement through an AXI-based HVM Access Port. For tasks that require integrated coprocessor control alongside data transfer, the versatile Andes Streaming Port (ASP) offers a suitable solution. By combining the ASP and HVM ports, the processor effectively doubles its memory bandwidth, enabling the loading of 2 vector data per cycle. Additionally, the AX45MPV supports the latest Andes Custom Extension (ACE), empowering customers to create their own RISC-V styled vector instructions. This feature can be utilized to accelerate nonlinear math functions like SoftMax on Transformer AI.

Dr. Charlie Su, President and CTO of Andes Technology, expressed his excitement about the AX45MPV’s potential in the AI and Machine Learning segments beyond the Cloud. He highlighted Andes’ extensive experience in serving datacenter AI customers since 2019 and emphasized the tailored nature of the AX45MPV for Large Language Models (LLMs). With the anticipated surge in generative AI applications in 2023, Dr. Su believes that the AX45MPV will take center stage in these domains.

Several customers from Asia and North America have already licensed the AX45MPV, while others are currently evaluating its capabilities. These customers span a wide range of applications, from cloud-based solutions to edge computing. The AX45MPV standard product package, without Linux support, is available immediately, while the advanced package with Linux support is expected to be available in Q4 2023.

Technology Explained

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SoC: A System-on-Chip (SoC) is a highly integrated semiconductor device that encapsulates various electronic components, including processors, memory, input/output interfaces, and often specialized hardware components, all on a single chip. SoCs are designed to provide a complete computing system or subsystem within a single chip package, offering enhanced performance, power efficiency, and compactness. They are commonly used in a wide range of devices, from smartphones and tablets to embedded systems and IoT devices, streamlining hardware complexity and facilitating efficient integration of multiple functions onto a single chip.