OPENEDGES achieves successful validation of 7nm HBM3 testchip, a major breakthrough.

OPENEDGES Technology and its subsidiary TSS have successfully developed and validated an HBM3 testchip, showcasing their expertise and positioning themselves as a leading memory subsystem IP vendor for chiplet designs.

Successful bring-up and validation of HBM3 testchip in 7 nm process technology
Utilization of state-of-the-art architecture for optimal performance
Ability to apply methodology to future chiplet designs

OPENEDGES Technology, Inc, the memory subsystem IP provider, has some exciting news to share. Its subsidiary, The Six Semiconductor Inc (TSS), has successfully brought-up and validated its HBM3 testchip in 7 nm process technology. Now, I know what you’re thinking: “What on earth is a testchip and why should I care?” Well, let me break it down for you.

HBM3 stands for High Bandwidth Memory 3, and it’s a technology that offers blazing-fast speeds and high capacity. The HBM3 testchip is like a prototype that allows engineers to test and validate the performance of the HBM3 memory subsystem before it goes into production. It’s a crucial step in the development process, and not many companies have been able to achieve this feat.

But OPENEDGES is proud to be one of the few companies that have successfully demonstrated an HBM3 memory subsystem in silicon. Farhad Haghighi Zadeh, TSS Principal Engineer and project lead for the HBM3 PHY and testchip, expressed his confidence in the engineering team’s capabilities, which allowed them to take on this challenging task.

Now, let’s talk about the HBM3 PHY. PHY stands for Physical Layer, and it’s responsible for handling the electrical signals that flow between the memory controller and the memory chips. The HBM3 PHY developed by OPENEDGES utilizes state-of-the-art architecture to ensure optimal performance even in the face of process, voltage, and temperature variations. It supports up to 16 independent and asynchronous channels, each with 2×32-bit DWORD pseudo-channels. In simpler terms, it’s designed to handle a lot of data at once and make sure it gets to where it needs to go without any hiccups.

What’s even more impressive is that the HBM3 PHY has additional features like fast frequency switching, transient error handling, and lane repair. Fast frequency switching allows for multiple frequency set points, which means the memory subsystem can adapt to different performance requirements. Transient error handling, on the other hand, ensures data integrity by using techniques like ECC (Error Correction Code) and parity checks. And finally, lane repair automatically detects and fixes any issues with the interconnects, making sure that everything runs smoothly.

Now, developing an HBM3 memory subsystem is no walk in the park. It’s a complex process that involves integrating the memory controller/PHY SoC (System-on-Chip) with the HBM3 die stack, silicon interposer, and package Substrate. There are thousands of tiny micro-bumps that need to be assigned, connected, and verified correctly. It requires careful planning and design to make sure everything fits together perfectly. And let’s not forget about the power and ground delivery, which needs to be top-notch to ensure optimal performance.

But here’s the exciting part: the methodology used in developing the HBM3 PHY testchip can be applied to future chiplet designs. chiplets are small, modular chips that can be combined to create complex systems. So, by mastering the development of an advanced memory subsystem chiplet, OPENEDGES is positioning itself as the go-to memory subsystem IP vendor for the chiplet space.

Richard Fung, CEO of TSS, expressed his pride in the successful bring-up of the HBM3 testchip and its outstanding performance. He also emphasized that OPENEDGES’ lineup of advanced memory subsystem IPs is perfect for anyone looking to build an IO chiplet with memory interfaces. Their memory controllers and PHYs are fully integrated, fully verified, and ready to be deployed in customers’ chiplet products.

Sean Lee, CEO of OPENEDGES Technology, added that the successful validation of the HBM3 testchip is not just a milestone but a testament to the value of their technology. They are committed to empowering their partners with superior performance and reliability.

So, there you have it. OPENEDGES Technology and its subsidiary TSS have achieved something remarkable with the successful bring-up and validation of their HBM3 testchip. It’s a testament to their expertise, dedication, and commitment to pushing the boundaries of memory subsystem technology. And with their proven design methodology and complete portfolio of memory subsystem IPs, they are ready to take on the chiplet space and revolutionize the way we think about memory interfaces.

OPENEDGES achieves successful validation of 7nm HBM3 testchip, a major breakthrough.

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