Next-Gen PCIe 7.0 Draft Unveiled: Lightning-Fast 512 GB/s Speeds via PCIe x16 by 2025

PCI-SIG has announced the release of version 0.5 of the PCI-Express 7.0 specification, marking the second draft of the spec and the final opportunity for PCI-SIG members to submit their new features. This update comes nearly a year after the initial Draft 0.3 specification was published, reaffirming that the development of the new standard remains on schedule for a 2025 release.

PCIe 7.0 is the upcoming interconnect technology for computers that promises to significantly boost data transfer speeds. With a data transfer rate of 128 GT/s per pin, it doubles the speed of PCIe 6.0 and quadruples that of PCIe 5.0. This means that a 16-lane (x16) connection will be capable of supporting an impressive 256 GB/sec of bandwidth in each direction simultaneously, excluding encoding overhead. These enhanced speeds will prove invaluable for future data centers, as well as applications in artificial intelligence and high-performance computing that demand even faster data transfer rates, including network data transfer rates.

To achieve these impressive data transfer rates, PCIe 7.0 doubles the bus frequency at the physical layer compared to its predecessors. However, it retains existing technologies such as pulse amplitude modulation with four level signaling (PAM4), 1b/1b FLIT mode encoding, and forward error correction (FEC) that were already utilized in PCIe 6.0. Additionally, the PCIe 7.0 specification focuses on improving channel parameters, reach, and power efficiency.

The engineers working on this standard face a significant challenge, as PCIe 7.0 requires doubling the bus frequency at the physical layer – a task that PCIe 6.0 managed to avoid with PAM4 signaling. Enhancing data signaling always comes with its own set of difficulties, and with PCIe 7.0, The PCI-SIG is once again tackling the complex task of improving the physical layer, this time aiming for a frequency of around 30GHz. The exact methods employed to achieve this goal, whether through smart signaling, retimers, or material improvements like thicker printed circuit boards (PCBs) and low-loss materials, are yet to be determined.

The next major step for PCIe 7.0 is the finalization of version 0.7 of the specification, known as the Complete Draft. This stage requires all aspects to be fully defined, and electrical specifications must be validated through test chips. Once this iteration is released, no new features can be added. PCIe 6.0 went through four major drafts before its finalization, so it is likely that PCIe 7.0 will follow a similar trajectory.

After the standard is finalized in 2025, it will still take a few years for the first PCIe 7.0 hardware to become available. While work on controller IP and initial hardware is already underway, the development process extends well beyond the release of the final PCIe specification.

Technology Explained

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PCIe: PCIe (Peripheral Component Interconnect Express) is a high-speed serial computer expansion bus standard for connecting components such as graphics cards, sound cards, and network cards to a motherboard. It is the most widely used interface in the computer industry today, and is used in both desktop and laptop computers. PCIe is capable of providing up to 16 times the bandwidth of the older PCI standard, allowing for faster data transfer speeds and improved performance. It is also used in a variety of other applications, such as storage, networking, and communications. PCIe is an essential component of modern computing, and its applications are only expected to grow in the future.