JEDEC Pushes DDR5 Memory Spec to 8800 MT/s, Bolsters Anti-Rowhammer Abilities

The updated DDR5 specification from JEDEC introduces faster data transfer rates and enhanced security features, potentially allowing for higher speed bins and mitigating vulnerabilities like rowhammer.

The inclusion of DDR5-8800 in the specification indicates industry agreement on its viability in terms of performance and cost.
The new specification introduces Per-Row Activation Counting (PRAC) to address rowhammer-style exploits, enhancing security.
The updated specification improves peak memory bandwidth by 37.5%, providing faster data transfer rates.

JEDEC, the standard setting organization, has released an updated specification for DDR5 memory, known as JESD79-JC5. This new specification introduces faster data transfer rates of up to 8800 MT/s (DDR5-8800) and includes enhancements in security features.

The inclusion of DDR5-8800 in the specification indicates that the industry agrees on its viability in terms of both performance and cost. This is supported by the introduction of the Self-Refresh Exit Clock Sync for I/O training optimization, which potentially enables higher speed bins.

In terms of timings, the JEDEC standard sets relatively loose values of CL62 62-62 for A-grade devices and CL78 77-77 for C-grade ICs. While the laws of physics governing DRAM cells have not significantly improved, memory chips still operate with similar absolute latencies. However, the new specification improves peak memory bandwidth by 37.5%.

It’s important to note that these timings primarily concern server vendors, and consumer memory manufacturers may be able to push the limits further for their XMP/EXPO-profiled memory. Overclockers have already achieved speeds as high as 11,240 MT/s with current-generation DRAM chips and CPUs, suggesting potential headroom for the next generation.

In terms of security, the updated DDR5 specification introduces Per-Row Activation Counting (PRAC) to address rowhammer-style exploits. PRAC keeps track of how often a memory row has been activated, allowing memory controllers to identify excessive activations that could lead to bit flips. This helps prevent rowhammer attacks by allowing rows to properly refresh and stabilize data.

While the specification does not explicitly mention rowhammer attacks, the description aligns with mitigating this vulnerability. The technique seems to be based on a recent Intel patent called “Perfect Row Hammer Tracking” (PRHT), which also addresses rowhammer attacks but comes with a performance cost due to increased row cycle time.

Additionally, the updated specification deprecates support for Partial Array Self Refresh (PASR) due to security concerns. PASR primarily focuses on power efficiency for mobile memory and may overlap with rowhammer vulnerabilities. However, this deprecation is unlikely to have a significant impact on consumer devices, as mobile devices are increasingly adopting low-power optimized LPDDR technologies.

Overall, the new DDR5 specification introduces faster data transfer rates and enhanced security features. It will be interesting to see how consumer memory manufacturers and overclockers push the boundaries further, while also considering the performance costs associated with mitigating vulnerabilities like rowhammer.

About Our Team

Our team comprises industry insiders with extensive experience in computers, semiconductors, games, and consumer electronics. With decades of collective experience, we’re committed to delivering timely, accurate, and engaging news content to our readers.

Background Information

About Intel:

Intel Corporation, a global technology leader, is for its semiconductor innovations that power computing and communication devices worldwide. As a pioneer in microprocessor technology, Intel has left an indelible mark on the evolution of computing with its processors that drive everything from PCs to data centers and beyond. With a history of advancements, Intel's relentless pursuit of innovation continues to shape the digital landscape, offering solutions that empower businesses and individuals to achieve new levels of productivity and connectivity.

Latest Articles about Intel

About JEDEC:

JEDEC is the global leader in the development of standards for the microelectronics industry. It was founded in 1958 as the Joint Electron Device Engineering Council to develop standards for the microelectronics industry. The organization's headquarters is located in Arlington, Virginia, United States. JEDEC sets standards for a wide range of technologies, including semiconductors, memory devices, integrated circuits, and more. Its standards are widely adopted and utilized throughout the industry to ensure compatibility and interoperability among various electronic devices and components.

Latest Articles about JEDEC

Technology Explained

DDR5: DDR5 (Double Data Rate 5) is the next generation of memory technology for the computer industry. It is a modern day improvement on earlier DDR technologies, with faster speeds, greater bandwidth and higher capacities. DDR5 enables higher resolution, seamless gaming experiences and faster data transfer rates, making it an ideal choice for high-performance computing and 4K gaming. With its greater RAM compatibility, DDR5 provides faster buffering times and raised clock speeds, giving users an improved overall work system. DDR5 is also optimized for multi-tasking, allowing users to multitask without experiencing a significant drop in performance, increasing the productivity of digital tasks. As an ever-evolving technology, DDR5 is paving the way for the computer industry into a new and powerful era.